TSMC CEO outlines efforts to enhance cost-effectiveness of High-NA EUV

The world's largest chipmaker is pumping the brakes on $400M-per-unit lithography tools, opting to squeeze more life out of current equipment until at least 2029.

Add us on Google by Editorial Team Jun. 4, 2026

TSMC Chairman C.C. Wei confirmed at the company’s annual shareholder meeting on June 4 that the foundry giant has purchased ASML’s High-NA EUV lithography systems, but strictly for research and development. The message was clear: these tools are not ready for the production floor, and the price tag is the main reason why.

Each High-NA EUV system costs approximately $400 million. That is roughly double the price of previous-generation EUV tools, which were already among the most expensive pieces of industrial equipment ever manufactured.

The $400 million question

High-NA EUV represents the next frontier in semiconductor lithography, the process of etching impossibly small circuit patterns onto silicon wafers. “NA” stands for numerical aperture, which determines how fine those patterns can be. A higher numerical aperture means smaller, more densely packed transistors, which means faster and more efficient chips.

TSMC’s R&D teams are now tasked with figuring out how to make these systems economically viable before they ever see a production wafer. Wei emphasized that the company is committed to enhancing cost-effectiveness ahead of any potential volume manufacturing.

The timeline for that transition is not exactly around the corner. TSMC Senior Vice President Kevin Zhang has previously stated that High-NA EUV technology is not expected to enter the company’s product line before 2029.

Making do with what works

Rather than rushing to adopt the newest and shiniest tools, TSMC is taking a decidedly pragmatic path. The company plans to rely on multi-patterning techniques using its existing low-NA EUV equipment to advance its upcoming chip nodes, including N2, A16, and A14.

Multi-patterning is essentially a workaround. Instead of printing a circuit pattern in one pass with a more advanced tool, you print it in multiple passes with the tool you already have. It is slower and adds complexity, but it avoids the capital expenditure of upgrading to entirely new systems at $400 million a pop.

The competitive landscape is not standing still

While TSMC is taking the cautious route, competitors are not waiting around. ASML has indicated it expects the first commercial chips utilizing High-NA EUV technology to roll out within months, with early adopters like Intel and SK Hynix leading the charge.

Intel, which has been aggressively retooling its manufacturing capabilities under its IDM 2.0 strategy, has been one of the most vocal proponents of High-NA EUV adoption. The company sees the technology as essential to regaining process leadership after years of falling behind TSMC and Samsung.

SK Hynix, meanwhile, is eyeing the technology for advanced memory chips, where denser patterning translates directly into higher capacity and better power efficiency.

Third, ASML’s position as the sole supplier of EUV lithography systems gives it extraordinary pricing power. The $400 million price tag for High-NA systems means any foundry adopting these tools needs extremely high utilization rates to make the economics work. TSMC’s decision to wait suggests the company does not yet see a path to those utilization levels for High-NA equipment.

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